Asynchronous binary array divider

ABSTRACT

This disclosure describes an asynchronous binary divider formed of an array of identical logic cells. Each cell includes a single bit binary subtractor and a selection gate. The array is connected to divisor, dividend, quotient and remainder registers. Divisor and dividend numbers are read into the divisor and dividend registers, respectively. The array of identical logic cells performs the division in parallel asynchronously and places the results of the division in the quotient and remainder registers for subsequent readout.

United States Patent 1 Wang [ ASYNCHRONOUS BINARY ARRAY DIVIDER [75Inventor: Gary Y. Wang, Wellesley Hills,

Mass.

[73] Assignee: The United States of America as represented bytheAdministrator of the National Aeronautics and'Sp'ace Administration,Washington, DC.

[22] Filed: July 1, 1969 [21] App]. No.': 838,278

[521 U.S.Cl. 235/164 51] Int. Cl. G06f7/54 [58] FieldofSearch 235/164,156

["56] 7 References Cited I UNITED STATES PATENTS 3,257,548 6/1966Fleisheretal. 235/164 3,378,677 4/1968 Waldecker et al 235/164 1 1 Apr.9, 1974 3,229,079 1/1966 Zink, Jr. 235/164 3,064,896 11/1962 Carroll etal 235/164 Primary Examiner-Felix D. Gruber Assistant Examiner-Davidl-LMalzahn' Attorney, Agent, 0r Firm-William l-l. Kingflohn R. Manning;Howard J. Osborn 5 7] ABSTRACT This disclosure describes an asynchronousbinary divider formed of an array of identical logic cells.'Each cellincludes a single bit binary subtractor and a selection gate. The arrayis connected to divisor, dividend, quotient and remainder registers.Divisor and dividend numbers are read into the divisor and dividendregisters, respectively. The array of..identicalf logic cells performsthe division in parallel asynchronously and places the results of thedivision-in thequotient and remainder registers for subsequent readout.

7 Claims, 4 Drawing PATENTEUAPR 91914 S4 S3 S2 S1 SHEEI 1 [IF 3 COLUMNS7 INVENTOR Gory Y. Wang i gamsvs FIG.I0.

QATENIEDAPR 9 I974 sum a of 3 3,803,393

ROWS

INVENTOR Gory -Y. Wang ATTORNEYS PATENTED 9 INVENTOR Gqry Y. Wang 1ASYNCIIRONOUS BINARY ARRAY DIVIDER ORIGIN OF THE INVENTION The inventiondescribed herein was made by an employee of the United States Governmentand may be manufactured and used by or for the Government forgovernmental purposes without the payment of any royalties thereon ortherefor.

BACKGROUND OF THE INVENTION This invention relates to digital computers,and more particularly to a new and improved asynchronous binary divider.Binary dividers suitable for use in computers to perform binary divisionare well known. Generally, prior art apparatus for performing binarydivision use controlled sequences of subtract-and-shift operations toperform the desired division. More specifically,

the normal method of operation of prior art binary division apparatus'isvery straight forward and, relatively, uncomplicated'The method is muchthe same as the method a person with pencil and paper uses to carry outdecimal division in long-hand by a sequence of conditional subtractionsand shifts. In general, this method requires that the person attempt todetermine the quotient digits by examining the divisor with relation tothe dividend or partial remainder. For example, in the case of twopositive binary numbers, the magnitude of the divisor (S) is comparedwith the magnitude of the divident or partial remainder (R) to determinethe proper quotient digit. If (S) e (R), a l is entered for the quotientdigit and (S) issubtracted from (R). In addition, the result is shiftedto the left one bit position to form a new partial remainder. If (S)(R), a zero is entered for the quotient digit and the previous partialremainder is shifted one bit position to the left to form a' new partialremainder. The following example more specifically illustrates thisprocedure:

.0 Quotient -1100 1st try (D)- (S) unsuccessful 10100 1100 2nd try '(R)(S) successful 1100 3rd try (R) (S) successful 1100 4th try (R) (S)unsuccessful 1000 Remainder The foregoing procedure can be mostaccurately described as an attempt to obtain a l for the quotient bit.If the first try is unsuccessful, the quotient bit must be a 0, sinceonly two alternatives are available. The anw re tqjth ct nesx p e areQuotient 0 5.

' 0.0110=%; and, Remainder (R)=0.00001 1732;

respect to the subtract-and-shift operations necessary to performdivision thereby speeding the overall operation of the divider.

7 It is a still further object of this invention to provide anasynchronous binary array divider formed of an array of identical logicelements virtually eliminating all complex control logic systemcircuitry that is needed to control prior art binary dividers.

And still another object of this invention is to provide an asynchronousbinary divider formed'of an array of identical logic elements therebyreducing cost and design effort and increasing'reliability.

SUMMARY or THE INVENTION In accordance with a principle of thisinvention, an asynchronous binary divider formed of an array ofidentical logic cells is provided. Divider, dividend, quotient andremainderv registers are connected to the array. In operation, divisorand dividend numbers are read into the respective divisor and dividendregisters. The array reads the number in the registers and per-' formsthe required subtract-and-shift division operations essentiallysimultaneously. The results of the simultaneous subtract-and-shiftdivision operations are placed in the quotient and remainder registersfor subsequent readout.

In accordance with a further principle of this invention, the logiccells of the array are eachformed of a single bit binary subtractor anda selection gate. And, each single bit binary subtractor and eachselection gate is formed of digital logic gates.

It will be appreciated from the foregoing summary of the invention thata binary divider that overcomes the prior art problems previouslydescribed is provided by the invention. Because the binary array dividerof the invention is formed of identical logic. cells, it can takeadvantage of well known Large Scale Integration (LSI) techniques. Oncethe dividend and divisor registers are loaded, the array cells begin towork in parallel, asynchronously without the need for any timing controlsequencing. After a small time delay- Le. the sum of circuit delays,both the quotient and the remainder are available to be loaded intoquotient and remainder. registers. Since the control circuitry necessaryfor controlling the division operations is simplified, performance andreliability are improved. In addition, because the array operatesessentially simultaneously as opposed to sequentially, division speed isimproved. Moreover, the repetitive pattern of the array allows modularexpansion to suit essentially any size of operands.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing objects and many of theattendant advantages of this invention will become more readilyappreciated as the same becomes better understood by reference to thefollowing detailed description when tractor suitable for use in theembodiment of the invention illustrated in FIGS. 1a and lb; and,

FIG. 3 is a block diagram of a selection gate suitable for use in theembodiment of the invention illustrated in FIG. 1. 1

DESCRIPTION OF THE PREFERRED EMBODIMENT For clarity and ease ofdescription, FIGS. 10 and 1b illustrate a 5 column X 4 row binary arraydivider made in accordance with the invention. However, it is to beunderstood that, within practical limitations, an asynchronous binaryarray divider formed in accordance with the invention can be made in anysize.

The embodiment of the invention illustrated in FIGS. 1a and 1b includes:an N stage dividend register 11; an N stage divisor register 13; an(N-l) stage quotient register 15; and, a 2(N-1) remainder register 17.For the particular configuration illustrated, the dividend register 11is a five stage register with the stages designated D D D D and D.,,with the D stage being the lowest order stage. The divisor register 13is also a five stage register with the stages designated S S S S and Swith the S stage being the lowest order stage. The quotient register 15is a four stage register with the stages designated Q Q Q and Q with thelowest order stage being Q And, the remainder register 17 is an eightstage register with the stages designated R R R R R.,, R R and R7 withstage R being the lowest order stage.

The embodiment of the invention illustrated in FIGS.

1a and 1b also includes an array 19 of N(Nl) identical logic cells,which can be denominated as Ci, j,, where i runs the gamut of integersfrom 0 to Nl and j runs the gamut of integers from 0 to N-2. In theillustrated embodiment the array 19 is in the form of a matrix havingfour rows and five columns read from top to bottom and right to left,respectively, for purposes of this description. That is, the followingdescription uses i and j subscript terminology and a (+1) added to asubscript means the next lower row or the next left column, as the casemay be. Each logic cell of the array comprises a single bit binarysubtractor 21 and a selection gate 23. A preferred embodiment of asingle bit binary subtractor is illustrated in FIG. 2 and hereinafterdescribed. In addition, a preferred embodiment of a selection gate isillustrated in FIG. 3 and hereinafter described.

Each single bit binary subtractor 21 includes three inputs: one input isa minuend input (M) and is derived either from the dividend register 11or from a selection gate of a higher AND-4; one logic cell. The higherorder selection gate 23 is one column to the right and one row up asviewed in FIGS. 1a and lb. The second input is a subtrahend input (S)and is derived from one of the stages of the divisor register 13. Thelowest order stage (S of the divisor register is connected to thesubtractors of the first, or rightmost, column of each row; the nexthigher order stage (8,) is connected to the next leftmost column of eachrow; etc. The third input to each single bit binary subtractor 21 is theborrow input (B) and is derived from the single bit binary subtractor ofthe next lower order column in the same row. It should be noted that inaccordance with conventional digital logic diagrams, the borrow input isillustrated as an arrow away from a particular subtractor, the arrowindicating where the borrow comes from, not where it goes.

The uppermost and rightmost (0,0 as illustrated in FIGS. la and lbsingle bit binary subtractor 21 receives its minuend input from the Dstage of the dividend register 11 and its subtrahend input from the Sstage of the divisor register 13. The next leftmost (1,0) subtractor inthe same row receives its minuend input from the D stage of the dividendregister 11 and its subtrahend input from the S, stage of the divisorregister 13.

This input arrangement continues until the leftmost subtractor of thefirst row receives its minuend input from the D stage of the dividendregister 11 and its subtrahend input from the 8 stage of the divisorregister 13.

The rightmost subtractor (0,1) of thenext row receives its minuend inputfrom the output of the selection gate 23 of the logic cell in a row notshown. In this example, as shown in FIG. 1, the rightmost logic cells inrows 1, 2, and 3 are subject to boundary constraints, i.e. all borrowsand minuends inputs are logical Os. In addition the borrow input of therightmost logic cell in the first row is a logical 0. This samesubtractor (0,1) receives its subtrahend input from the S stage of thedivisor register 13. The second subtractor in the second row receivesits minuend input from the output of the selection gate of the logiccell in the first row, first column; and, its subtrahend input from theoutput of the 8, stage of the divisor register 13. In a similar manner,the subtractors 21 of the remaining rows are connected to the selectiongates of preceeding rows and the stages of the divisor register.

Each single bit binary subtractor has two outputs, one output is theborrow output (B) for the next higher order subtractor. The borrowoutput of the leftmost subtractor of a particular row is the quotientfor that row and is connected to the input of one of the stages of thequotient register 18. The borrow output of the leftmost subtractor 21 ofa particular row is also connected to each selector gate of that row asillustrated in FIG. 3 and hereinafter described. The other output ofeach single bit binary subtractor is a difference output (D) and isconnected to one input of the selector gate of the same logic cell ofthe array. I

Each selection gate 23 has three inputs and one output. As previouslydescribed, first and second of the inputs are respectively derived fromthe input and output of the subtractor 21 forming a part of the samelogic cell. The third input is derived from the borrow output of theleftmost borrow network of the same row, whereby for example, each ofthe selection networks having one input responsive to D D ,,differencesignals is responsive to the B borrow signals. The outputs of theselection gates deriving outputs M where j3 runs the gamut from 1 toN-l, (i.e., M M M and M and M where i runs the gamut from 1 to N-l,(i.e., M,,.,, M M and M are connected to different stages of theremainder register 17, the M signal being coupled to R the M signalbeing coupled to R etc. The outputs of the other selection gates 23 areconnected to the next left and next lower subtractor to form the minuendinput for as previously described. I

that subtractor,

.in accordance with the invention and comprises a difference part 31 anda borrow part 33. The difference part comprises four AND gatesdesignated AND-l,

AND-2, AND-3, and AND-4; one OR gate designated OR-l; and, one invertergate designated I-l. Each AND gate is a three input AND gate and the ORgate is a four input OR gate.

For ease of description,i and j subscripts are used in FIGS. 2 and 3 andthe following description, where i is a column index subscript and j isa row index subscript and the'addition of a -H to a particular i or jmeans that the particular output goes to an input in the next column orrow, as the case'may be. The B inputs to the AND gates illustrated inFIG. 2 are borrow inputs from lower order logic elements as illustratedin FIG.- 1 and previously'described. The M inputs are minuend inputs.either from the dividend register 11 in the case of the first row oflogic cells or higherorder selector subsections 23, for all of thesubsequent rows also as illustrated in FIG. 1 and previously described.

AND-l has a1? input, anS, input and an M input; AND-2 has ail, input, anS, input'and an M input; AND-3 has a B input, an? input, and an M input;and AND-4 has a B input, an Sg input, and an-Mf input. The outputs ofAND-l, AND-2,-.AND-3,and AND-4 are separately connected to the fourinputs of OR-l. The output of OR-l is a difference output, is designatedDm JH and is connected to a selector subsection of the type illustratedin FIG. 3 and'hereinafter described. In addition, the output of OR-l isconnected through 1-] so as to form aD 4+1 output.

riiatafistipm 553m "altimeter initiated FIG. 2 comprises; three ANDgates designated AND-5 AND-6, and AND-7; an OR gate designated OR-2;and, an inverter designated 1-2. The AND 'gates are two input. ANDgates, and the OR gate is a threeinput OR gate. AN D- 5 has a B and anS, input; AND-6 has a B and an M input; and, AND-7 has an S, and a minput. The outputs of AND-5, AND-6 and AND-7 are separately connected tothe three inputs of QR-.2. The output of OR-2 is a B output and isconnected to the next higher order subtractor as the B input. In addi*tion, the output from OR-2 is connected through I-2 so as to form aEoutput which forms the'B input for subtractor illustrated in FIG. 2:

Borrow out 2+1 .1)

Minued i.i)

Borrow in Subtrahend (B (Si tiongate and comprises: two AND. gatesdesignated decimal) 1n the quotient register and the formation of 6AND-8 and AND-9; one OR gate designated OR-3; and, one inverterdesignated 1-3. The AND gates are two input AND gates and the OR gate isa two input OR gate. For purposes of this description, the borrowoutputs of the leftmost subtractors which, as illustrated in FIG. 1, areconnected to the quotient register and also to the selection gates aredesignated B t and p AND-8 basi and o nn um; and AND-9 has B t and Minputs. The outputs of AND-8 and AND-9 are connected to the inputs OR-3.The output of OR-3, designatedM can therefore be written as D B B M andis connected as the M 7 input to the subtractor of the next row andcolumn as illustrated in FIGS. 1a and 1b. In addition, the output fromOR-3 is applied through [-3 to create an M output. This latter output isconnected as the H input to the next appropriate row and columnsubtractor subsection. The various stages of the quotient register 15are set to logical lsby the negation (Lei of the leftmost borrows of thecorresponding rows.

Turning tibial/"to a dE sci-iptibn bf the 'sperauaaarthe" embodiment ofthe invention illustrated in the figures, as will be appreciatedfromviewing FIGS. .la' and 1b, all of the selection gatesin a particular roware com{ monly controlled by the quotient bit or borrow circuit of thelast subractor in that row. If B,, J for. that row is a binary zero (0),the results of .the subtractors in that row are fed throughthe selectiongates and used as the partial remainder. for the next row. However, whena borrow occurs (i.e., B is a-binary one (1) at the last subtractor of aparticular row, the results of the subtractors in that row are by-passed'and the partial remainder of the previous row is used-as the partialremainder for the next row. The displacement of one col umn bit positionbetween rows, corresponding to one bit left shift of the partialremainder, is accomplished automatically due to the arrangement of thearray. I For illustrativepurposes, tiifihifiihiscfisd in theintroduction to this disclosure is illustrated in FIGS." la and 16.Specifically,.a binary dividend of 0.0101 (5/16 in decimal) is'read intothe dividend register 11 by any suitable, well known, control means.Similarly,

a binary divisor of 0.1100 (3/4 in decimal)'is read into the divisorregister'13 by any suitable means. In addition, the following set ofboundary conditions is set up for the edges of the array;- 7 4 ...ta ou.y to m. h second q m ntbiwh shi .th borrow (F that controls theselection gates'of the.

second row. This action continuesthrough the third (2), and fourth(3)rows. The end result of these operations is the formation of the binarynumber 0.01 10 we in the binary number 090001000 1/32 in decimal) in theremainder .register. I v I W It will be appreciated from the foregoingdescription that the subtract-and-shift operations described in thediscussion of this example in the introduction to the disclosure are allcarried out by the binary array. However, these operations are carriedout essentially simultaneously as opposed to serially. Hence, theasynchronous binary array divider of the invention is considerably morerapid in operation than prior art binary dividers whereinsubtract-and-shift operations are carried out serially. Morespecifically, it will be appreciated by those skilled in the art andothers that the foregoing sequence of operations is essentiallysimultaneous as opposed to serially. Contrawise, prior art systemsgenerally perform the required subtract-and-shift operations in series,thereby performing the overall division operation relatively slowly.Hence, this invention considerably speeds up the overall divisionoperation.

It will also be appreciated by those skilled in the art that theinvention has other advantages over prior art binary dividers. Forexample, because the invention utilizes an array of identical logiccells it can be created in modular form and easily expanded, ifnecessary. Also many different types of logic cellsmay be used. Inaddition, the control circuitry necessary for the operation of theinvention is greatly reduced over prior art dividers, hence, the cost ofmanufacturing a divider to carry out a particular size of divisionoperations is greatly reduced. Moreover, due to the reduction in thenumber of control components, the reliability of the overall system isimproved.

What is claimed is:

1. An asynchronous binary array divider comprising a dividend registerhaving N binary stages each storing a binary minuend signal denominatedas M where i runs the gamut of integers from to N-l a divisor registerhaving N binary stages, each storing'a binary signal denominated as 8,,where j runs the gamut of integers from 0 to Nl a matrix having N(N-lcells, each of said cells being denominated as C where i runs the gamutof integers from 0 to N-l; and jl runs the gamut of integers from 0 toN2, each of said cells including a difference network for deriving asingle bit binary difference signal denominated as D for cell C, aborrow network for deriving a single bit binary signal denominated as B-for cell C, and indicative of whether a borrow condition exists inresponse to the subtraction operation performed by the differencenetwork of cell C and a selection network for deriving a single bitminuend binary signal denominated as M for cell C said differencenetwork for cell C being responsive to the borrow signal B the divisorregister signal S, and the minuend signal M said borrow network for cellC being responsive to the divisor signal S; the minuend signal M and theborrow signal B and the selection network for cell C being responsive tothe minuend signal M the difference signal D and the borrow signal B 2.The divider of claim 7 further including a quotient register having (Nl)binary stages, each of said stages of the quotient register beingseparately responsive to the B signals derived from the (Lycells.

3. The divider of claim 1 further including means for feeding borrowsignals of predetermined value to cells C and means for feeding minuendsignals of predetermined value to cells'C where 12 runs the gamut ofintegers from 1 to N-2.

4. The divider of claim 1 wherein the difference network of cell Cincludes means for deriving its D output signal in accordance with:

i+1,j1+l EJS m Em J im an Ml iJI J iJI 5. The divider of claim 1 whereinthe borrow network of cell C, includes means for deriving its B outputsignal in accordance with:

BHIJI ur 3 ur 141+ 1.51

6. The divider of claim 1 wherein the selection network of cell Cincludes means for deriving its MMJIH output signal in accordance with:

7. The divider of claim 1 further including a remainder register having2(N-l) binary stages, the first (N-l of the stages of the remainderregister being separately responsive to the M minuend signals derivedfrom cells C the remaining (N-l) of the stages of the remainder registerbeing separately responsive to the M M3 minuend signals derived fromcells C where:

i runs the gamut of integers from 1 to N-l;

j runs the gamut of integers from 1 to N-l and j., runs the gamut ofintegers from 0 to N-2.

1. An asynchronous binary array divider comprising a dividend registerhaving N binary stages each storing a binary minuend signal denominatedas Mi,0, where i runs the gamut of integers from 0 to N-1, a divisorregister having N binary stages, each storing a binary signaldenominated as Sj, where j runs the gamut of integers from 0 to N-1, amatrix having N(N-1) cells, each of said cells being denominated asCi,j1, where i runs the gamut of integers from 0 to N-1; and j1 runs thegamut of integers from 0 to N-2, each of said cells including adifference network for deriving a single bit binary difference signaldenominated as Di 1,j/ 1 for cell Ci,j1, a borrow network for deriving asingle bit binary signal denominated as Bi 1,ji for cell Ci,j1 andindicative of whether a borrow condition exists in response to thesubtraction operation performed by the difference network of cell CN,j1,and a selection network for deriving a single bit minuend binary signaldenominated as Mi 1,ji 1 for cell Ci,j1; said difference network forcell Ci,j1 being responsive to the borrow signal Bi,j1, the divisorregister signal Sj and the minuend signal Mi,jl, said borrow network forcell Ci,j1 being responsive to the divisor signal Sj the minuend signalMi,j1 and the borrow signal Bi,j1; and the selection network for cellCi,j1 being responsive to the minuend signal Mi,jl the difference signalDi 1,j1 1 and the borrow signal BN,j1.
 2. The divider of claim 7 furtherincluding a quotient register having (N-1) binary stages, each of saidstages of the quotient register being separately responsive to the BN,j1signals derived from the CN 1,ji cells.
 3. The divider of claim 1further including means for feeding borrow signals of predeterminedvalue to cells CO,j1, and means for feeding minuend signals ofpredetermined value to cells C0, j2, where j2 runs the gamut of integersfrom 1 to N-2.
 4. The divider of claim 1 wherein the difference networkof cell Ci,j1 includes means for deriving its Di 1,j1 1 output signal inaccordance with: Di 1,j1 1 Bi,j1SjMi,j1 + Bi,j1SjMi,j1 + Bi,j1 Sj, Mi,j1+Bi,j1SjMi,j1
 5. The divider of claim 1 wherein the borrow network ofcell Ci, j1 includes means for deriving its Bi 1,j1 output signal inaccordance with: Bi 1,j1 Bi,j1 Sj + Bi,j1 Mi,j1 + Sj Mi,j1
 6. Thedivider of claim 1 wherein the selection network of cell Ci,jl includesmeans for deriving its Mi 1,j1 1 output signal in accordance with: Mi1,j1 1 BN,j1 Di 1,j1 1+BN,j1 Mi,j.
 7. The divider of claim 1 furtherincluding a remainder register having 2(N-1) binary stages, the first(N-1) of the stages of the remainder register being separatelyresponsive to the Mi1,N-1 minuend signals derived from cells Ci1,N-1,the remaining (N-1) of the stages of the remainder register beingseparately responsive to the MN,j3 minuend signals derived from cells CN1, j4, where: i1 runs the gamut of integers from 1 to N-1; j3 runs thegamut of integers from 1 to N-1 and j4 runs the gamut of integers from 0to N-2.